1. Field of the Invention
The present invention relates to an address conversion circuit and an address conversion system. More particularly, the present invention relates to an address conversion circuit and an address conversion system for use with a memory which is provided with a redundant memory array for relieving defective memory cells so as to facilitate ensuring memory capacity.
2. Description of the Related Art
FIG. 6 illustrates a conventional address conversion system. The address conversion system includes a CPU 3, a memory control circuit 110 connected to the CPU 3, and a plurality of memories 102 connected to the memory control circuit 110.
Memory is sold typically with a particular capacity (eg. 40 MB). This capacity is ensured, meaning that even if some memory cells are defective, the memory will still provide the designated capacity.
Each memory 102 includes a normal memory array (not shown) having a capacity corresponding to the total capacity of the memory 102.
The memory 102 of the conventional address conversion system includes, in addition to the normal memory array, a redundant memory array (not shown) and a redundancy decision circuit 103 for ensuring the total capacity of the memory 102 even when the normal memory array includes a defective memory cell (not shown). When the defective memory cell is to be accessed, the redundancy decision circuit 103 replaces a physical address corresponding to the defective memory cell by another physical address corresponding to a memory cell in the redundant memory array.
FIG. 7 illustrates the memory 102 and the memory control circuit 110 of the conventional address conversion system in greater detail. For sake of simplicity, only one memory 102 is shown in FIG. 7. The memory control circuit 110 includes an address conversion section 101. The redundancy decision circuit 103 in the memory 102 includes a comparison circuit 102A and a defective address storing section 102B.
The address conversion circuit 101 converts a logical address received from the CPU 3 to a physical address corresponding to a memory cell in the memory 102. The comparison circuit 102A compares the physical address received from the address conversion circuit 101 with a defective address stored in the defective address storing section 102B.
When the physical address received from the address conversion circuit 101 matches the defective address, the memory cell to be accessed is a defective memory cell. In such a case, the redundancy decision circuit 103 replaces the physical address received from the address conversion circuit 101 by a redundant address corresponding to a memory cell in the redundant memory array and accesses the memory cell in the redundant memory array instead of the defective memory cell.
When the physical address received from the address conversion circuit 101 does not match the defective address, the memory cell to be accessed is a normal memory cell. In such a case, the redundancy decision circuit 103 accesses the memory cell in the normal memory array corresponding to the physical address received from the address conversion circuit 101.
As described above, the conventional address conversion system includes the redundancy decision circuit 103 in each memory 102 so that the redundancy decision is made within the memory 102 for ensuring the total capacity of the memories 102 even when a defective memory cell exists. In such an address conversion system, however, the access speed to the memory decreases for the reason described below.
FIG. 8A illustrates a first processing method used in a memory access operation by the conventional address conversion system. FIG. 8B illustrates a second processing method used in a memory access operation by the conventional address conversion system.
Referring to FIG. 8A, in the first processing method, the redundancy decision circuit 103 first performs a process P1 (over a time period T1) for determining whether a physical address received from the address conversion circuit 101 matches a defective address stored in the defective address storing section 102B and, if there is a match, replacing the physical address with a redundant address. Subsequent to the process P1, a process P2 (over a time period T2) is performed for accessing a memory cell corresponding to either the physical address from the address conversion circuit 101 (a normal address) or the redundant address by which the physical address from the address conversion circuit 101 is replaced.
Referring to FIG. 8B, in the second processing method, the process P1 is performed as described above while performing, in parallel with the process P1, a process P3 (over a time period T3) for making an access to a certain point in an access path to the memory cell corresponding to the normal address.
Subsequent to the process P1, if the redundancy decision circuit 103 in the memory 102 determines that the physical address received from the address conversion circuit 101 matches the defective address, a process P4 (over the time period T2) is performed to access the memory cell corresponding to the redundant address with which the physical address from the address conversion circuit 101 is replaced.
If the redundancy decision circuit 103 determines that the physical address received from the address conversion circuit 101 does not match the defective address, the redundancy decision circuit 103 does not have to perform the address replacement process. In such a case, after a wait time T5 (=T1xe2x88x92T3), a process P6 (over a time period T6=T2xe2x88x92T3) is performed to complete access to the normal address part of which has been made during the process P3.
In either the first processing method or the second processing method, the accessing time (a time period from the time when the memory 102 receives a physical address to the time when the addressed data is accessed and output) necessarily includes the time period T1 (for the redundancy decision circuit 103 to determine whether the physical address received from the address conversion circuit 101 matches a defective address and, if there is a match, replace the physical address by a redundant address).
Conventionally, in order to meet the demand to design a memory such that the memory independently ensures the total capacity thereof, the redundancy decision circuit 103 has been provided in the memory 102. As a result, the time period T1 (for determining whether the physical address received from the address conversion circuit 101 matches a defective address and, if there is a match, replacing the physical address by a redundant address) has been consumed by the memory 102. This is disadvantageous, however, in terms of reducing the time required by the address conversion system to access the memory 102.
According to one aspect of this invention, an address conversion circuit is provided for converting a logical address to a physical address and outputting the physical address to a memory, the memory including a normal memory array and a redundant memory array wherein a defective address corresponding to a defective memory cell in the normal memory array is replaced by a redundant address in the redundant memory array so as to ensure total memory capacity of the memory. The address conversion circuit includes: an address conversion section for converting the logical address to a first physical address in the normal memory array and outputting the first physical address; a defective address storing section for storing the defective address corresponding to the defective memory cell in the memory; and a redundancy decision circuit for, in response to a decision that the first physical address matches the defective address, replacing the first physical address with a second physical address corresponding to the redundant address and sending the second physical address to the memory.
In one embodiment of the invention, the redundancy decision circuit includes: a comparison section for comparing the first physical address output from the address conversion section with a defective address stored in the defective address storing section and outputting a comparison result; a replacement section for replacing the first physical address in the normal memory array by the second physical address corresponding to the redundant address; and a selector for selectively outputting to the memory one of the first and second physical addresses based on the comparison result.
In one embodiment of the invention, the redundancy decision circuit includes a mode signal output section for outputting a mode signal to the memory based on the comparison result.
According to another aspect of this invention, an address conversion system includes: a CPU for outputting a logical address; an address conversion circuit for receiving the logical address, converting the logical address to a physical address and outputting the physical address; and a memory for receiving the physical address and accessing a memory cell corresponding to the physical address. The memory includes a normal memory array and a redundant memory array wherein a defective address corresponding to a defective memory cell in the normal memory array is replaced by a redundant address in the redundant memory array so as to ensure total memory capacity of the memory. The address conversion circuit includes: an address conversion section for converting the logical address to a first physical address in the normal memory array and outputting the first physical address; a defective address storing section for storing the defective address corresponding to the defective memory cell in the memory; and a redundancy decision circuit for, in response to a decision that the first physical address matches the defective address, replacing the first physical address by a second physical address corresponding to the redundant address and sending the second physical address to the memory.
In one embodiment of the invention, the redundancy decision circuit includes: a comparison section for comparing the first physical address output from the address conversion section with a defective address stored in the defective address storing section and outputting a comparison result; a replacement section for replacing the first physical address in the normal memory array by the second physical address corresponding to the redundant address; and a selector for selectively outputting to the memory one of the first and second physical addresses based on the comparison result.
In one embodiment of the invention, the address conversion circuit further includes a mode signal output section for outputting a mode signal to the memory based on the comparison result.
In one embodiment of the invention, the memory includes a plurality of memory chips.
When a defective memory cell is to be accessed, the address conversion circuit of the present invention replaces the physical address corresponding to the defective memory cell by another physical address corresponding to a memory cell in a redundant memory array, and outputs the redundant address to the memory.
Thus, when using the address conversion circuit of the present invention, the time period consumed for determining whether a received physical address matches a defective address and, if there is a match, replacing the physical address by a redundant address is not included in the accessing time (a time period from the time when the memory receives a physical address to the time when the addressed data is accessed and output).
As a result, it is possible to reduce the time required to access the memory while ensuring total capacity of the memory even when a defective memory cell exists in the memory.
Thus, the invention described herein makes possible the advantages of (1) providing an address conversion circuit which can reduce the time required to access a memory while ensuring total memory capacity even when a defective memory cell exists in the memory; and (2) providing an address conversion system incorporating such an address conversion circuit.